1. Field of the Invention
The present invention relates to a semiconductor memory apparatus having a refresh test circuit, and more particularly, to an improved semiconductor memory apparatus having a refresh test circuit, capable of separately testing the refresh of a memory cell.
2. Description of the Background Art
FIG. 1 is a block diagram of a semiconductor memory apparatus having a refresh test circuit according to the conventional art.
As shown therein, the apparatus includes a data input/output buffer 1 for a temporary storage so as to output the data stored in a memory cell, a write control unit 2 for receiving a write enable signal WEB and controlling the data input/output buffer 1, a row address buffer 3 and a column address buffer 6 for temporarily storing address signals A0-An, a refresh address counter 4 for refreshing memory cells, a refresh control unit 5 for controlling the refresh address counter 4, a row block decoder 7 and a plurality or row decoders 8a-8e for receiving the row address applied to the row address buffer 3 and generating a real address for accessing memory cells, a column decoder 10 for receiving the column address applied to the column address buffer 6 and generating a real address for accessing the memory cell, a plurality of sense amplifier arrays 12a, 12b for amplifying the externally applied data and storing the same in the memory cell, a plurality of memory cell arrays 9a-9e provided with the memory cells selected by the plurality of row decoders 8a-8e and the column decoder 10, and a control unit 11 for receiving a row address strobe signal RASB and a column address strobe signal CASB and controlling respective units accordingly.
The thusly constituted conventional semiconductor memory apparatus having a reference test circuit will now be described.
First, when address signals A0-An are applied to the row address buffer 3 and the column address buffer 6, the row decoders 8a-8e select word lines by the row address applied to the row address buffer 3 and the column decoder 10 outputs a column selection signal (that is, Y selection signal YS) by the column address applied to the column address buffer 6 and selects corresponding memory cells of the memory cell arrays 9a-9e.
Here, the number of address signals A0-An and the number of row decoders 8a-8e or the number of signals applied to the column decoder 10 are determined depending upon a product specification (for example, x4, x8, x16, etc.) and memory concentration (for example, 4M, 16M, 64M, etc.). Also, as the number of words of a memory increases, so does the number of signals applied to the decoder for thereby increasing the number of word lines and bit lines which determine the address of memory cells.
The block diagram shown in FIG. 1 illustrates a 16M.times.4/4K refresh product, wherein the number of signals applied to respective portions is calculated such that the number of address signals is 12 (A0-A11) and the output number M of the refresh address counter 4 determined by the number of refresh cycle also becomes 12.
In addition, the input of the row block decoder 7 for selecting memory cell arrays 9a-9e is determined according to a composition of memory cell arrays or sensitivity of a sense amplifier and power consumption. In general, the number of word lines cared by one of the decoders 8a-8e ranges from 256 to 512 so that the increase of the memory concentration causes the number increase of the memory cell arrays 9a-9e, whereby the number of address signals allotted to the row block decoder 7 is increased as well. Accordingly, if the number of word lines of the memory cell arrays is set as 512, the number of address signals for decoding the row decoder becomes 9 (AX0-AX8) and the block decoding address number becomes 3 (AX9-AX11) and the number of memory cell arrays becomes 8.
The thusly constituted semiconductor memory apparatus becomes a 64M (16M words*4 bits) memory apparatus having 23 memory cell arrays, 212 word lines and 212 bit lines.
FIGS. 2A through 2C illustrate a test method of respective refresh tests for a semiconductor memory apparatus.
The refresh tests include a pause (static) refresh test and a disturb refresh test. In the pause refresh test, data is simply written in all the memory cells and read after a predetermined time period, wherein the test has some difference from a real application environment of the memory cells and it checks basic characteristics of DRAM memory cells generating constant discharge.
Meanwhile, the disturb refresh test is tested such that the background data is written in all the cells while the data in the ambient memory cells is changed, or the ambient word lines and bit lines are continuously activated during the refresh test time period.
As shown in FIG. 2B, the disturb-1 refresh test is the simplest disturb refresh test, wherein even numbers or odd numbers of word lines are continuously activated during the refresh time tREF so as to check data.
Also, as shown in FIG. 2C, the disturb-2 or disturb-3 refresh test is implemented with regard to respective word lines (here, 2M lines) driven by the row decoders 8a-8e for activating the word lines of the memory cell arrays 9a-9e.
However, as the memory integration of memory cells are increased and memory cell processing becomes further difficult, so the refresh characteristic of the memory cells becomes further deteriorated.
In addition, if integration of a semiconductor memory apparatus is increased, the number of word lines and column selection lines for driving respective memory cells is also increased, so that the number of cycles for testing memory cells and the time for testing is exponentially increased.